Devices incorporating heavily defected semiconductor layers

ABSTRACT

The structure and growth method are disclosed for a novel heterojunction diode structure. The invention exploits the Fermi level pinning properties of dislocations and defects in compound semiconductors to achieve heterojunctions with nonlinear current-voltage characteristics despite highly defected, polycrystalline, or amorphous semiconductors. The invention enable new diode, photodetector, and transistor devices to be implemented using highly lattice-mismatched semiconductors. The invention additionally enables thin film diodes, photodetectors, and transistors to be realized.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from U.S. Provisional Pat. No.60/640,724 filed Dec. 31, 2004, “Diodes incorporating heavily defectedsemiconductor layers.”

FIELD OF THE INVENTION

This invention relates generally to the fields of device physics andmicroelectronics, particularly to the semiconductor materials, design,structure, and fabrication of diodes, transistors and circuitscontaining them.

BACKGROUND AND LIMITATIONS OF THE PRIOR ART

Junction diodes form the basis of a wide range of electronic devices.Their nonlinear current versus voltage characteristics make them usefulas switches, rectifiers, electrical and optical signal detectors, andother microelectronic devices. Junction diodes can be used to modulatethe channel conductivity in a field effect transistor structure.Junction transistors can be formed by a series connection of twoback-to-back diodes, with the bias on the middle connection used tomodulate the series current. Common junction diodes includemetal-semiconductor contacts (Schottky diodes), PN (p-type-n-type)junction diodes, nN (n-type-N-type) isotype heterojunction diodes, MIM(metal-insulator-metal), NIN (n-type-insulator-n-type), PIP(p-type-insulator-p-type), and PIN (p-type-insulator-n-type) diodes.Common junction transistors include the Metal-Semiconductor Field EffectTransistor (MESFET), the Junction, Field Effect Transistor (JFET), theBipolar Junction Transistor (BJT), the Heterojunction Bipolar Transistor(HBT), and the metal-base transistor.

When diodes contain crystalline or amorphous semiconductor layers,defects within the semiconductors often degrade performanceunacceptably, notably by increasing leakage currents and by acting asresistive shorts across the junction. Diodes formed with nearly perfectsemiconductor single-crystals are therefore commonly preferred to thealternatives for high-performance applications.

For many applications, however, it is essential or desirable to producejunction diodes in materials that are not nearly perfect singlecrystals. For example, production of junction diodes using arbitrarypairs of semiconductor materials would give access to desirableproperties, including availability of the semiconductor material,turn-on voltage, switching speed, blocking current, or other aspectsimportant to semiconductor junctions. If the lattice-mismatch andthickness of the layers are such that the critical thickness forpseudomorphic growth is exceeded, lattice relaxation will occur, with acorresponding nucleation and generation of a high density ofdislocations to accommodate the lattice strain. For lattice-mismatchedjunctions, dislocation densities in excess of 1×10⁷ cm⁻² are commonlyobserved, and dislocation densities at the interface between two highlylattice-mismatched semiconductors can be 1×10¹² cm⁻³ or more. (See HTsukamoto, E-H Chen, J M Woodall, and V Gopal, “Correlation of defectprofiles with carrier profiles of InAs epilayers on GaP,” Appl. Phys.Lett., 78(8) pp. 952-954 (12 Feb. 2001).) Such dislocations aregenerally electrically active (S D Lester, F A Ponce, M G Craford and DA Steigerwald, “High dislocation densities in high efficiency GaN-basedlight-emitting diodes,” Appl. Phys. Lett. 66, pp. 1249-1251 (6 Mar.1995) and J M Woodall, G D Pettit, T N Jackson, and C Lanza,“Fermi-Level Pinning by Misfit Dislocations at GaAs Interfaces,” Phys.Rev. Lett., 51(19), pp 1783-1786, (7 Nov. 1983); V Gupta;. E-H Chen, E PKvam, and J M Woodall, “Behavior of a new ordered structural dopantsource in InAs/(001) GaP heterostructures, J. Vac. Sci. Technol. B17(4), pp. 1767-1772 (July/August 1999)).

The electrical activity of such dislocations acts to pin the Fermi levelnear a fixed position in the band gap, which makes it difficult to useextrinsic doping to achieve desired free-carrier concentrations. Thedefect states associated with dislocations, grain boundaries, and othersemiconductor surfaces are usually sufficient to pin the Fermi level toa fixed value relative to the conduction band (or valence band) edge.This Fermi level pinning property is generally characteristic of a givensemiconductor material and relatively insensitive to growth method orimpurity composition(see M J Caldas, A Fazzio, and A Zunger, “Auniversal trend in the binding energies-of deep impurities insemiconductors,” Appl. Phys. Lett., 45(6), p. 671-673 (September 1984);W Walukiewicz, “Fermi level dependent native defect formation:Consequences for metal-semiconductor and semiconductor-semiconductorinterfaces,” J. Vac. Sci. Technol. B. 6(4), pp. 1257-1262(July/August1988); and S Tiwari and D J Frank, “Empirical fit to banddiscontinuities and barrier heights in III-V alloy systems,” Appl. Phys.Lett. 60(5), pp. 630-632 (February 1992)).

Fermi level pinning determines the position of the Fermi level positionat surfaces and defects relative to the conduction band edge (or valenceband edge). In many semiconductors, this Fermi level pinning propertyplaces the Fermi level midway between the conduction band minimum andthe valence band maximum, inside the forbidden band gap (M J Cohen, M DPaul, D L Miller, J R Waldrop, and J S Harris, Jr., “Schottky barrierbehavior in polycrystal GaAs,” J. Vac. Sci. Technol., 17(5), pp. 899-903(September/October 1980); J Levinson, F R Shepherd, P J Scanlon, W DWestwood, G Este, and M. Rider, “Conductivity behavior inpolycrystalline semiconductor thin film transistors,” J. Appl. Phys.53(2), pp. 1193-1202 (February 1982)).

Estimated Fermi level pinning positions of various semiconductors arelisted in Table I. As can be seen from the table, most semiconductorsexhibit Fermi level pinning within the forbidden band gap, and hence ahigh density of pinning states generally cause such semiconductors toexhibit low free-carrier concentrations and mostly insulatingcharacteristics.

Some semiconductors (e.g. InAs and InN) exhibit Fermi level pinningpositions above the conduction band minimum (see: HH Wieder, “Surfaceand interface barriers of In_(x)Ga_(1-x)As binary and ternary alloys”,J. Vac. Sci. Technol. B 21(4), p. 1915-1919 (July/August 2003)), so ahigh density of pinning states causes these materials to be degeneratelydoped n-type and highly conductive. Similarly, some semiconductors (e.g.Ge) exhibit Fermi level pinning positions below the valence bandmaximum, and therefore a high density of pinning states causes thesematerials to be degenerately doped p-type and highly conductive. TABLE IElectron affinity and Fermi level pinning position for selectedsemiconductors. The electron affinity [E_(C)], valence band [E_(V)], andFermi level [E_(F)] are with respect to the vacuum level. All values arein electron-volts (eV). Negative values for E_(F) − E_(C) indicate thatthe Fermi level pinning position is above the conduction band minimum(highly degenerate). Similarly negative values for E_(V) − E_(F)indicate that the Fermi level pinning position is below the valencemaximum (highly degenerate). Electron Valence affinity Band Band Fermilevel Material [E_(C)] gap [E_(V)] [E_(F)] E_(F) − E_(C) E_(V) − E_(F)Silicon 4.05 1.12 5.17 4.8 0.75 0.37 Germanium 4.0 0.66 4.66 4.8 0.8−0.14 GaAs 4.07 1.424 5.494 4.8 0.7 0.7 InP 4.4 1.35 5.75 4.8 0.4 0.95InAs 4.9 0.35 5.25 4.8 −0.1 0.45 InN 5.5 0.75 6.25 4.8 −0.7 1.45

Ut s typically the case that the only effective way to achieve effectiveextrinsic doping in polycrystalline or heavily defected material is todevelop techniques to reduce the defect density to below 10⁷ cm⁻², suchas is often achieved using metamorphic growth techniques or byincreasing the grain size so that the density of grains is less than 10⁷cm⁻².

Some commercially significant applications ordinarily requiring use ofhighly defected or amorphous materials include thin-film diodes such asthose deposited on amorphous or polycrystalline substrates, diodes usingsemiconductors with a large amount of lattice-mismatch either to eachother, or to a substrate, semiconductor material combinations thatnaturally result in a high density of dislocations such as more than10⁶, 10⁷, or 10⁸ dislocations/cm²), or polycrystalline semiconductorssuch as semiconductors with more than 10⁷ grains/cm².

Applications for diodes formed from highly defected or amorphousmaterials include thin-film displays, thin-film electronics, switches,rectifiers for rectennas, as one of-the junctions in a junctiontransistor, as both junctions in a junction transistor, as the gatejunction in a field effect transistor, and in three-dimensionalintegrated circuits where additional layers of circuitry are depositedon top of active circuitry.

Diodes using semiconductors with a high defect density may be grown onamorphous, polycrystalline, or single-crystal substrates, and allowintegration of a wider range of semiconductors than is available inlattice-matched systems. High defect densities are generally observedfor semiconductor active regions which are grown to a thickness largerthan the pseudomorphic limit such that lattice relaxation occurs,causing the generation of more than 10⁷ dislocations/cm² to accommodatethe strain. High defect densities are also generally observed forsemiconductor active regions grown on amorphous or polycrystallinesubstrates, generally forming polycrystalline layers with more than 10⁷grains/cm². Note that highly defected semiconductors also includes allclasses of amorphous semiconductors, where defect densities may be hardto quantify and the material is characterized as having poor long rangeorder. Active regions of a diode are defined as those regions within thedepletion region of a diode, as well as those regions within about 100nm of either the depletion region or the junction. Active regions of adiode also include any region of the diode where minority carriers (inbipolar devices) or hot carriers (in hot electron devices) are used totransport current.

MIM (metal-insulator-metal) diodes are well known in the prior art (seeSze, Physics of Semiconductor Devices, p. 553, 1981), where theinsulator region is typically a wide band gap insulator such as SiO₂,AlO₂ or other metallic oxides, Si₃N₄ or other nitrides, or otheramorphous or crystalline insulators, and the metal regions can be nearlyany metal. MIM diodes generally rely on tunneling through the insulatorregion, and therefore generally exhibit low current densities and lowreliability.

Single-crystal diodes including nIn diodes are also well known in theprior art (S L Feng, J Krynicki, M Zazoui, J C Bourgoin, P Bois, and ERosencher, “Electron transport through GaAlAs barriers in GaAs,” J.Appl. Phys., 74, p. 341 (1993)). Single-crystal diodes rely onlattice-matched semiconductor layers to achieve high electricalperformance, and therefore are limited to a narrow range ofsemiconductors that are lattice-matched and where a suitablesingle-crystal substrate is available.

Lattice-mismatched single-crystal semiconductors diodes are also knownin the prior art (G Martin, S Strite, J Thornton, and H Morkoc,“Electrical properties of GaAs/GaN/GaAssemiconductor-insulator-semiconductor structures,” Appl. Phys. Lett. 58,p. 2375 (1991)). Such devices rely on high-temperature epitaxial grownof high-quality epitaxy, and takes advantage of the unique properties ofcertain heterojunctions such as GaN on GaAs growth, where the latticeratio of cubic GaN to cubic GaAs is 4.5 Å/5.65 Å≅4/5, which allows anearly perfect sub-lattice spacing (J Narayan and B C Larson, “Domainepitaxy: A unified paradigm for thin film growth,” J. Appl. Phys., 93,pp. 278-285 (1 Jan. 2003).). Nearly perfect sub-lattice spacing allowshigh-quality GaN to be grown on GaAs and vice versa without thegeneration of a large density of threading dislocations. Furthermore,threading dislocations in semiconductors such as GaN appear to besignificantly less electrically active then defects in other III-Vsemiconductors such as GaAs (S D Lester, F A Ponce, M G Craford, and D ASteigerwald, “High dislocation densities in high efficiency GaN-basedlight-emitting diodes,” Appl. Phys. Lett., 66(10), pp 1249-1251 (6 Mar.1995).).

Prior art, high-performance heterojunction semiconductor devicesgenerally require two materials to be lattice-matched or nearlylattice-matched. Lattice-mismatched materials like Si/SiGe andInGaAs/GaAs can be used only if the lattice-mismatched layers are thinenough to be pseudomorphic, so exhibit a low density of dislocations.

High-performance heterojunction bipolar transistors (HBTs) are wellknown in the prior art. HBTs only work well in a limited range ofsemiconductor materials systems where devices can be manufactured withhigh-quality out of single-crystals, and work poorly where thesemiconductor materials are not available as single-crystals with lowdefect densities. Highly perfect single-crystals are necessary becausecrystalline imperfections such as point defects, dislocations, grainboundaries, and others act as recombination sites which reduce amicroelectronic device's performance, including reduced gain and shortermean time to failure.

There are several materials systems which could, in principle, yieldHBTs with superior performance to today's best. For example, InAs, InSb,and related In-rich III-V semiconductors (including alloys of thesesemiconductors with other III-V semiconductors) offer unprecedentedelectrical transport characteristics, because their band structurediscourages scattering from the primary (Γ) conduction band valley intothe L and X valleys, and because the effective mass of electrons movingin the Γ valley is anomalously low. A low effective mass provides highelectron mobility in general, and for hot electrons a long meanfree-path. High mobility and low resistivity are also advanced by thefact that these semiconductors can be heavily doped. A similar class ofhigh-performance semiconductors is available in certain narrow band gapII-VI materials, most notably HgCdTe and related compound semiconductorswhose band gap is less than about 0.5 eV. These materials can exhibitelectron mobilities in excess of 10⁴ cm/s and large separation betweenthe primary conduction band valley and satellite valleys. Table IIsummarizes key properties of selected compound semiconductors, such asthe high electron mobilities and peak velocities of InAs and InSb. TABLEII Key properties of fast III-V semiconductors Electron mobility forSeparation low doped, btwn Gamma Thermal single- valley and Expectedpeak velocity Electron Band crystals nearest local velocity electronsMaterial mass gap (eV) (cm²/V-s) minimum (eV) (cm/s) (cm/s) InAs 0.0230.35 30,000 0.73 >1.0E8  7.7E7 InSb 0.014 0.51 80,000 0.51 ?? 9.8E7 InP0.08 0.59 5,000 0.59 2.5E7 3.9E7 InN 0.11 0.75 3,000 4.0E7 3.4E7 GaAs0.63 1.42 8,500 0.29 2.0E7 4.4E7

What the table does not show is that InAs, InN, and InSb suffer severaldrawbacks which limit the ability to use them in HBTs. These include alow band gap and poor materials quality. The low band gap causes highleakage currents in bipolar devices because the thermal generation ratefor minority carriers is very high in semiconductors with a narrow bandgap. The poor materials quality stems from the fact that suitablyhigh-quality, lattice-matched (or nearly lattice-matched)heterojunctions and insulating substrates are not readily available. Toachieve high-performance, InAs and InSb must be grown onlattice-mismatched, semi-insulating substrates, which is difficult andgenerally results in a significant density of threading dislocationsthat further limit performance.

Several other prior art transistor structures offer different advantagesfrom HBTs. A hot electron transistor (HET) injects electrons withenergies of at least several times kT higher than thermal electrons atthe band edge. In the case of bipolar transistors, hot electrons areproposed in numerous prior art publications as a means of increasing theperformance of an HBT, although in practice, only a minor improvementover non-hot electron HBTs is observed. In addition, HBTs that use hotelectrons still suffer from the same limitation of other HBTs asdescribed above, namely limitations due to the requirements forultra-high-quality single-crystals.

Several unipolar HET devices have been proposed (See S. M. Sze, Physicsof Semiconductor Devices, Chapter 9, John Wiley & Sons, New York, 1981)such as the metal base transistor usingmetal-insulator-metal-insulator-metal (MIMIM) orsemiconductor-metal-semiconductor (SMS) structures, and single-crystalsemiconductor HET devices. Currently, none of these unipolar HET deviceshave achieved commercial success.

Metal base transistors have not achieved commercial success for twoprimary reasons (S. M. Sze and H. K. Gummel, “Appraisal ofSemiconductor-Metal-Semiconductor Transistor,” Solid-State Electronics,9, pp. 751-769, 1966):

-   -   1. The mean free path of a hot electron in a metal is short, so        too many hot electrons lose too much of their excess energy to        be able to surmount the base-collector barrier. These carriers        are lost, which reduces the HET's gain.    -   2.Quantum mechanical reflections arise from the large difference        in electron velocity on either side of base-collector junction.        These reflections represent a significant loss mechanism,        particularly when trying to exploit base and collector materials        with markedly distinct band structures.

Unipolar hot electron transistors using single-crystal semiconductorshave also been an area of extensive research (see A F J Levi, T H Chiu,“Room-temperature operation of hot-electron transistors,” Appl; Phys.Lett. 51, 28 Sep. 1987, pp. 984-986; T H Chi and A F J Levi, “Electrontransport in an AlSb/InAs/GaSb tunnel emitter hot-electron transistor,”Appl. Phys. Lett. 55, 30 Oct. 1989, pp. 1891-1893; M Heiblum and M VFischetti, “Ballistic hot-electron transistors,” IBM J. Res. Develop.34(4), July 1990, pp. 530-549). Single-crystal semiconductors exhibitsignificantly longer mean free scattering lengths but lower conductivitythan metals. The longer mean free scattering length allows thicker baseregions to be used, and the lower conductivity requires thicker baseregions in order to maintain low base resistance. In addition, using asingle-crystal semiconductor heterojunction at the base collectionjunction greatly reduces the quantum mechanical reflection coefficientbecause of the similarity of the band structures of most semiconductors.Indeed, Levi argues that it may be possible to make the quantummechanical reflection coefficient at the base-collector junctionnegligible by using techniques similar to anti-reflection coatings inoptics. However, prior art unipolar hot electron transistors usingsingle-crystal semiconductors have been limited to using the samematerials as conventional bipolar HBTs, which result in the followingprimary shortcomings:

-   -   1. Base resistance is not significantly improved over that of an        HBT due to doping and mobility limitations of the materials        used. While a unipolar HET uses a n-type semiconductor base        region, which typically exhibits an order of magnitude higher        mobility than the p-type semiconductor base region of an HBT,        materials limitations often limit the doping density in unipolar        HETs to an order of magnitude below that used bipolar HBTs,        resulting in similar base sheet resistance. This limitation        means that single-crystal unipolar HETs do not significantly        outperform conventional HBTs; because the base thickness of the        single-crystal unipolar HET must be similar to that of an HBT in        order to achieve the same base resistance. While base transit        time can be reduced in single-crystal Unipolar HET (hot        electrons are generally faster than thermal electrons), the base        transit time does not generally limit the performance of an HBT,        so single-crystal Unipolar HETs do not achieve significantly        higher speed than an HBT.    -   2. Due to the fact that the base region of a single-crystal        Unipolar HET is relatively thick, a significant fraction of the        electrons scatter and lose enough energy that they cannot        surmount the base-collector junction barrier, resulting in low        gain.    -   3. Quantum mechanical reflections at the base collector        heterojunction still occur because the requirement of        lattice-matching constrains matching the hot electron velocity        across the junction.    -   4. The requirement for a high-quality, single-crystal and        pseudomorphic materials has greatly limited the ability to use        those semiconductor materials best suited to hot electron        transistors. For example, InAs is nearly an ideal semiconductor        for the base region of a Unipolar HET, and HETs using InAs have        been demonstrated (see Levi references above). However, because        the only semiconductor with a close lattice-match to InAs are        GaSb, AlSb, and related semiconductors, performance is        significantly compromised. In such lattice-matched structures,        it is not possible to set the energy of the hot electrons        injected from the emitter arbitrarily (due to fixed barrier        heights between the emitter and base caused by the limited        choice of materials), as well as fixing the barrier height        between the base and collector: The hot electron energy must be        far enough above the base-collector barrier energy to achieve        efficient collection across this junction). While tunneling        emitter contacts (see M. Heiblum and M. V. Fischetti) and        barrier-lowering using reverse biasing at the base-collector        junction may be used to modify the intrinsic barrier heights,        such solutions only work for a limited range of bias voltages,        which in turn limits the utility of such transistors for many        applications. In addition, the use of antimonides greatly        complicates the manufacturing process, and generally results in        poor yields and high costs. Furthermore, since the choice of        materials for the collector region is constrained, it also        limits performance. Indeed, the collector transit time generally        limits the performance of a junction transistor. For example, a        collector with GaSb is typically lower performance than with        GaAs, InGaAs, InAlAs, or InP.

Semiconductor crystals grown on non-lattice-matched substrates generallyexhibit high density (more than 10⁷ cm⁻²) of dislocations, whichaccommodate the strain and lower the total energy of the system. Thesedislocations are generally associated with electrically active defectstates, which can act as donor or acceptors (or both). The energyassociated with these states can be anywhere within the forbidden bandgap, as well as above the conduction band minimum or below the valenceband maximum of the semiconductor.

Similarly, semiconductor crystals are grown on amorphous ornon-single-crystal substrates are generally amorphous, orpolycrystalline with a high density of grains (typically more than 10⁷cm⁻²). The defects in amorphous material and the grain boundaries inpolycrystalline material exhibit electrically active states that may actas donors, or acceptors (or both), and the energy associated with thesestates can be anywhere within the forbidden band gap, as well as withinthe conduction band or valence band of the semiconductor.

SUMMARY OF THE INVENTION

The invention enables high-performance semiconductor devices to beachieved without requiring ultra-low defect densities. Specifically, theinvention enables a wide range of junction diodes, and devices usingjunction diodes to be achieved where the active layers of the device arenot lattice-matched and are thicker than the pseudomorphic limit,resulting in layers that exhibit dislocation densities larger than 10⁸cm⁻², grain densities larger than 10⁸ cm⁻², and/or exhibit amorphouscharacteristics.

An object of the invention is to allow the use of heavily defected,polycrystalline, or amorphous semiconductors to be used for junctiondiodes despite the presence of Fermi level pinning in these materialsthat prevents effective extrinsic doping.

Another object of the invention is to form junction diodes with lowleakage currents despite using defected materials.

Another object of the invention is to form junction diodes in materialssystems that are not lattice-matched.

Another object of the invention is to produce NIN heterojunction diodeswhere one or both of the N regions are not lattice-matched to the Iregions.

Another object of the invention is device structures incorporating suchjunction diodes. These device structures include nonlinear circuitelements, switches, rectifiers, rectennas, optical detectors,transistors and other multi-junction devices, such as:

NIN Photodetectors:

-   -   i. Band-to-band absorption in the I region is readily detected        as a change in conductivity between the two n-type sides of the        device (photoconductive detection).    -   ii. Defect level-to-band absorption in the I region can be        achieved. This is particularly useful for long wavelength IR        detection. Absorption can be improved by increasing the density        and occupancy of traps in the I-region. The resultant absorption        can be detected as a change in conductivity between the two        n-type sides of the device (photoconductive detection).    -   iii. Defect level-to-band absorption in the I region may also        make use of the change in conduction through the defect states        in the I-region: if the states are nearly all filled with        electrons, conductivity is low because conductivity occurs via        hopping of holes. Absorption changes the concentration of holes,        and the resultant conductivity change is readily detectable.        Similarly, if the states are all empty (and can accept        electrons), hopping conduction of electrons can        occur-introduction of electrons into these states via optical        absorption will result in an increase in conductivity.    -   iv. Absorption in an N region can be detected via an internal        photoemission process, where absorption adds sufficient energy        to push an electron over the NI conduction band offset barrier,        and results in a measurable change in the conductivity between        the two n-type sides of the device.    -   v. Avalanche gain in the I region can be used to provide a        high-performance gain mechanism. For thin I regions, ionization        can be primarily determined by the width of the I region and        electron and hole feedback will be minimized, resulting in a        very low excess noise factor. This effect has been shown for a        number of thin gain region avalanche photodiodes.    -   vi. Photoconductive gain can be achieved in N1-I-N2-I-N1        devices, by storing charge in the internal (N2) node, causing a        persistent change in conductivity in the outer two N-type        regions (N1), persisting until the stored charge is annihilated        by a recombination event.    -   vii. Repeating several periods of NI (i.e. 1 repeat would be        NIN, 2 repeats would be NININ, 3 repeats would be NINININ . . .        ) allows increased absorption to be achieved despite the fact        that the N & I regions are thin enough to ensure ballistic        transport—very fast devices, high gain, etc.    -   viii. Avalanche gain can make use of n periods to achieve        periodic gain in the I-regions of the device, leading to high        gain and low noise    -   ix. NININ version of nipi devices (using high fields in the        I-region to effectively lower the band gap through Stark shift        and/or real space transfer, etc.)

Note that all of the NIN devices described above can be verticalstructures (three layer stack) or horizontal structures: N on top of I,where lithographic patterning of the N region is used to create lateralNIN structures.

NIN Electronic Devices:

-   -   i. Diodes and rectifiers (preferred embodiment). Note that        diodes and rectifiers can be used as nonlinear devices, as        switches, and as junctions in transistor structures.    -   ii. Three terminal devices:        -   a. (N1-I-N2)—use N1 as a channel region (with 2 contacts,            one for source, and one for drain) and N2 as a gate control.            Modulation of the gate control bias causes a change in            conductivity of the channel region via the field effect,            allowing the structure to be operated as a field-effect            transistor.        -   b. N1-I1-N2-12-N3 hot electron transistor, where the N2            region is the base region of a hot electron transistor.            Changing the bias on N2 causes a corresponding change in the            current between contacts to N1 and N3.    -   iii. NINININ devices. Adding more junctions can be used to        produce additional devices, such as Thyristors.

Optoelectronic Devices. Whether Photodetector or Non-Detector:

-   -   i. Use the high electrical fields possible in NIN and n-repeat        patterns for optoelectronic switching.    -   ii. Use NIN structure inside DBR mirror structure. Modulating        the bias would modulate the reflectivity by changing the optical        index of refraction.    -   iii. Filling or emptying the deep level states in the I layer to        change its refractive index in an optoelectronic modulator        device.    -   iv. Filling or emptying the deep level states in the I layer to        change its absorption, allowing an absorption modulator to be        produced.

Another object of the invention is to control the conductivity of thedefect states (dislocations and/or grain boundaries) by doping of thesemiconductor so as to substantially fill all of the states such thathopping conduction through defect states is suppressed. Similarly,doping can be used to substantially empty all of the defect states toprevent hole conduction.

Thin Film Devices:

Due to the fact that the “N” regions can use a class of semiconductorsthat are capable of exhibiting both high conductivity and high electronmobilities, including InAs, InGaAs, InP, InAsP, InN, InSb, and anycombination of these materials, it is possible to make thin film versionof the above devices. The thin films may use amorphous,nano-crystalline, or polycrystalline layers for both the N and the Iregions, with the added requirement that the N regions be chosen fromthose semiconductors that exhibit good amorphous or polycrystallineproperties, typically arsenides, phosphides, antimonides, and nitrideswhere at lest 25% of the atoms in the material are indium. There are nosuch requirements for I regions, because many highly defectedsemiconductors will exhibit mostly insulating properties due to theirFermi level pinning properties, which generally place the Fermi levelnear the middle of the forbidden band gap.

To prevent leakage current through the mid gap defect states fromdominating device performance, conductivity through these defect statesshould be as low as possible, which can be achieved by choosingmaterials with a low conductivity along grain boundaries ordislocations, or by using doping to suppress conduction along thesestates. Alternative means of suppressing conduction are also envisioned,including using multi-layer I structures (such asGaAs/Al_(0.5)Ga_(0.5)As/GaAs, GaA/In_(0.5)Al_(0.5)As/GaAs orn⁺-GaAs/p⁺-GaAs/n⁺-GaAs/p⁺-GaAs, etc) to block conduction through defectstates. In addition, thicker I regions may be used which should furtherreduce the leakage current.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 shows the preferred embodiment. FIG. 1A shows the epitaxial layerstructure, FIG. 1B shows the energy band diagram, and FIG. 1C shows theexperimental current-voltage characteristics.

FIG. 2 show several alternative embodiments. FIG. 2A shows the layerstructure of one alternative embodiment with asymmetrical rectifyingcharacteristics. FIG. 2B shows the layer structure of a differentalternative embodiment with asymmetrical rectifying characteristics.FIG. 2C shows the experimental current-voltage characteristics of thealternative embodiment shown in FIG. 2B.

FIG. 3A show the layer structure of an alternative embodiment used as aphotodetector. FIG. 3B shows the zero bias band diagram of the layerstructure of FIG. 3A. FIG. 3C shows the band diagram of the layerstructure of FIG. 3A under bias.

FIG. 4A shows the layer structure of an alternative embodimentconsisting of a polycrystalline NIN junction. FIG. 4B shows anotherlayer structure of an alternative embodiment consisting of apolycrystalline NIN junction.

FIG. 5A shows the layer structure of a lateral NIN diode in accordancewith the invention. FIG. 5B shows how the layer structure of FIG. 5A canbe fabricated into a lateral NIN diode.

FIG. 6A shows the layer structure of a field effect transistor where thegate junction is formed in accordance with the invention. FIG. 6B showshow the layer structure of FIG. 6A can be fabricated into a field effecttransistor.

FIG. 7A shows the layer structure of a thin film transistor inaccordance with the invention. FIG. 7B show how the layer structure ofFIG. 7A can be fabricated into a FET device.

FIG. 8A shows the band diagram of a hot electron transistor inaccordance with the invention. FIG. 8B show the layer structure of a HETin accordance with the invention.

FIG. 9A shows an alternative embodiment of the invention, a hot electrontransistor using GaAs emitter, an InAs base, and an In_(0.80)Al_(0.20)Ascollector on a GaAs substrate. FIG. 9B shows another HET structure inaccordance with the invention. FIG. 9C shows a thin film HET inaccordance with the invention. FIG. 9D shows an alternative thin filmHET in accordance with the invention. FIG. 9E shows another alternativethin film HET in accordance with the invention. FIG. 9F shows anotheralternative thin film HET in accordance with the invention.

DETAILED DESCRIPTION OF THE FIGURES

Reference is now made to FIG. 1A, which shows the layer structure of thepreferred embodiment of the invention. On GaP substrate 101 was grownlayer 103, consisting of a thickness 153 of 1000 nm of InAs doped n-typewith 1×10¹⁹ cm⁻³ silicon using molecular beam epitaxy (J C P Chang, T PChin, and J M Woodall, “Incoherent interface of InAs grown directly onGaP(001), Appl. Phys. Lett. v. 69, p. 981 (1996)). Due to the 11%lattice-mismatch between InAs and the GaP substrate 101, there will be ahigh density of threading dislocations at interface 111. These threadingdislocations rapidly annihilate during the growth of layer 103,resulting in an approximate threading dislocation density of 1-10×10⁹cm⁻² on the InAs side of interface 112 (H Tsukamoto, E -H Chen, J MWoodall, and V Gopal, “Correlation of defect profiles with carrierprofiles of InAs epilayers on Gap,” Appl. Phys. Lett. 78, p. 952(2001)). On top of the InAs layer 103 was grown GaAs layer 105 to athickness 155 of 20 nm. Due to the 7% lattice-mismatch between GaAs andInAs, GaAs layer 105 is expected to immediately relax, producing anetwork of edge dislocations, as well as a threading dislocation densitygreater than 1×10¹⁰ cm⁻². On top of GaAs layer 105 is grown a secondInAs layer 107 to a thickness 157 of 50 nm. InAs layer 107 is dopedn-type with a silicon doping density of 1×10¹⁹ cm⁻³.

We note here that layers 103, 105, and 107 were grown by MBE usinggrowth conditions that promote planar, layer by layer growth, andtherefore are single-crystal. Due to the large amount oflattice-mismatch between each of the layers, strain relaxation occursvery rapidly, resulting in a high density of misfit and threadingdislocations. It is worthwhile to note that these dislocations introducedeep level defects in GaAs layer 105, with the energy level of thedefect being near mid gap, while dislocations introduce shallow donorsstates in InAs layers 103 and 107 (M J Cohen, M D Paul, D L Miller, J RWaldrop, and J S Harris, Jr., “Schottky barrier behavior in polycrystalGaAs,” J. Vac. Sci. Technol., 17, p. 899 (1980); V Gopal, E-H Chen, E PKvam, and J M Woodal, “Behavior of a new ordered structural dopantsource in InAs/(001) GaP heterostructures,” J. Vac. Sci. Technol. B. 17,p. 1767 (1999)). Therefore, the GaAs layer 105 is semi-insulating, whilethe InAs layers 103 and 107 are highly conductive, n-typesemiconductors.

Reference is now made to FIG. 1B, showing a band diagram of the layerstructure of FIG. 1A with no applied bias. In FIG. 1B, the y-axis 168 isenergy while the x-axis 169 is the vertical position within thestructure. The valence band maximum is represented by 161, theconduction band minimum is represented by 163, and the Fermi level isrepresented by 165. Due to the heavy doping of the InAs layers (both dueto the intentional silicon doping and the unintentional doping due tothe dislocations), the InAs is highly degenerate with the Fermi level atleast 0.1 eV above the conduction band edge 163 in layers 103 and 107.The energy difference between the Fermi level 165 and the conductionband edge in layer 107 is 171. The potential barrier between the Fermilevel 165 and the conduction band edge 163 in layer 105 is 172. Sincethe Fermi 165 is pinned to the trapping energy of the dislocations inlayer 105, the potential barrier height 172 is about 0.7 eV.

Reference is now made to FIG. 1C, showing the experimentally measuredcurrent-voltage characteristics of the layer structure shown in FIG. 1A.Ohmic contacts are made to layers 107 and 103, and mesa isolation wasused to etch a circular mesa into layer 107 to define the device area.The diameter of the mesa is 40 μm. In FIG. 1C, the y-axis 198 is currentwhile the x-axis 199 is voltage. Curve 191 is the experimentallymeasured current between the ohmic contacts to layers 107 and 103. Thedevice shows excellent rectifying characteristics, with a turn onvoltage between 0.5- and 1.0 Volts. Due to the degenerate doping of then+InAs layers and the mid-gap Fermi level pinning of the i-GaAs layer,the structure resembles a n-type-insulator-n-type (NIN) ormetal-semiconductor-metal structure (MSM) structure, and the I-V curveis similar to what would be expected, exhibiting back to back diodecharacteristics. The metal-semiconductor (n++-InAs to i-GaAs) andsemiconductor-metal (i-GaAs to n⁺⁺-InAs) junctions act as diodes, withone diode reverse biased and one diode forward biased for all biasconditions. The reverse biased diode limits the current, and thereforecurrent only flows when the reverse biased diode begins to break down.This break down may be due to avalanche break down in the i-GaAs layer105, tunneling from one of the “metal” layers (107 or 103) into orthrough the i-GaAs layer 105, possibly including trap assisted tunnelingfrom dislocation states in the i-GaAs layer 105. Due to the fact thatthe turn-on voltage shown in FIG. 2C is 0.5-1.0 volts, the electronsinjected from one layer 105 into the other layers (107 or 103) will haveexcess energy, and may be used for ballistic transport through layer 107or 103. Such hot electron transport may be useful in multiple junctiondevices such as hot electron transistors or multiple junctionphotodetectors.

Reference is now made to FIG. 2A, which shows an alternative embodimentof the invention consisting of a single NI junction. Layer 201A is asemi-insulating GaAs substrate. On top of layer 201A is grown N-typeside of the junction layer 203A to a thickness 253A of 1000 nm and dopedn-type with silicon to a doping density of 1×10¹⁸ cm⁻³. Those skilled inthe art will observe that different doping levels and differentsemiconductors can be used in layer 203A. On top of N-type layer 205A isgrown I-type layer 205A, consisting of undoped GaAs grown to a thickness255A of 100 nm. On top of the I-type layer 205A is grown a graded layer206A, where smooth compositional grading is used to grade fromIn_(0.8)Ga_(0.2)As (near the junction with layer 207A) to GaAs (near thejunction with layer 206A). Layer 206A is undoped and grown to a totalthickness 256A of 100nm. On top of layer 206A is grown a n⁺In_(0.8)Ga_(0.2)As contacting layer 207A, grown to a thickness 257A of100 nm, and doped 1×10¹⁸ cm⁻³ using silicon. Graded layer 206Afacilitates injection of electrons from contact 207A into the I-typelayer 205A, and therefore acts as an ohmic contact to the conductionband of layer 205A. This means that the diode formed between layers 207Aand 203A acts as a single NI junction, and will therefore be rectifyingwith a high degree of asymmetry (in contrast to the NIN diode of FIG. 1,which acts as back to back diodes, and therefore is symmetrical unlessthe two N regions are different).

Reference is now made to FIG. 2B, which shows an experimentalrealization of an alternative embodiment of the invention consisting ofa single NI junction. Layer 201B is a n-type GaP substrate. On top oflayer 201B is grown buffer layer 202B, consisting of a thickness 252B of500 nm undoped Gap (adjacent to substrate 201B), followed by 20 periodsof a strained layer supperlattice consisting of pairs of alternating 5nm InAs and 5 nm In_(0.75)Al_(0.25)As layers (total thickness if 200nm). On top of buffer layer 202B is grown an N-type contact layer 203B,which is used to form ohmic contact to the I-type side of the junction.Layer 203B in n-type InAs grown to a thickness 253B of 1500 nm and dopedn-type with silicon to a doping density of 2×10¹⁹ cm⁻³. On top of layer203B is grown the graded transition layer 206B, which provides a smoothcompositional grading from InAs (near the junction with layer 203B) ton-In_(0.65)Al_(0.35)As (near the junction with layer 207B). Thethickness 256B of transition layer 206B is 200 nm, and the layer isnominally undoped. On top of layer 206B is grown layer 207B, which formsan abrupt heterojunction between layers 206B and 207C. Layer 207Bconsists of undoped InAs grown to a thickness 257B of 10 nm. Layer 207Bis grown at a reduced substrate temperature (nominally 300° C.) in orderto insure that the interface between layers 207B and 206B is abrupt. Ontop of layer 207B is grown the n-type side of the device 207C. Layer207C consists of n-type InAs doped with silicon to a doping density of2×10¹⁹ cm⁻³ and grown to a thickness 257C of 100 nm.

Reference is now made to FIG. 2C, showing the experimentally measuredcurrent-voltage characteristics of the layer structure shown in FIG. 2B.Ohmic contacts are made to layers 203B and 207C, and wet chemicaletching was used to etch a circular mesa into through layers 207C, 207B,and 206B to define the device area. The diameter of the mesa is 28 μm.In FIG. 2C, the y-axis 298 is current, with the plot showing a maximumcurrent of 4 A/cm² and a minimum current of −4 A/cm². The x-axis 299 isvoltage, with a minimum voltage of 1.5 V and a maximum voltage of 0.5V.Curve 281 is the experimentally measured current between the ohmiccontacts to layers 207C and 203B. The device shows excellent asymetricalrectifying characteristics, with a turn-on voltage near 0.2 V, and lowerreverse bias currents for voltages between −0.5 and 0 Volts. Due to thedegenerate doping of the n⁺ InAs layers 207B and 207C and the mid-gapFermi level pinning of the i-In_(0.35)Al_(0.65)As layer 206B, thestructure resembles a n-type-insulator or metal-semiconductor diodestructure, and the I-V curve is similar to what would be expected for aSchottky diode with a low barrier height.

Reference is now made to FIG. 3A, showing the layer structure of analternative embodiment consisting of a series connection of 10 NIjunctions, which can be used as a photodetector. On top of glasssubstrate 301 is grown layer 303, consisting of a thickness 353 of 100nm of n⁺-type InAs doped with silicon to a density of 1×10¹⁸ cm⁻³. Ontop of layer 303 is grown layer 305 consisting of 10 periods ofalternating layers of 50 nm of n⁺ InAs doped with silicon to a densityof 1×10¹⁸ cm⁻³ and 50 nm of i-GaAs that is nominally undoped. The totalthickness 355 layer 305 is 1000 nm. On top of layer 305 is grown the topcontacting layer 307, consisting of a thickness 357 of 100 nm of n⁺ InAsdoped with silicon to a density of 1×10¹⁸ cm⁻³.

Reference is now made to FIG. 3B, showing the zero bias band diagram ofFIG. 3A, showing energy 398 as a function of depth 399 with the layer.The conduction band edge is represented by 388, and the valence bandedge is represented by 389. Transistion 321 shows how absorption of aphoton with sufficient energy can promote an electron from the valenceband of the InAs layer 361A to an excited state in the conduction bandof InAs layer 361A with sufficient energy that it can surmount thepotential barrier of the conduction band offset to the adjacent GaAslayer 362A and can therefore be collected as a photo current.Transistion 323 shows how free-carrier absorption of a photon withsufficient energy can promote a thermal electron from the conductionband of the InAs layer 361A to an excited state in the conduction bandof InAs layer 361A with sufficient energy that it can surmount thepotential barrier of the conduction band offset to the adjacent GaAslayer 362A and can therefore be collected as a photo current. Transition325 shows how absorption of a photon with insufficient energy canpromote an electron from the valence band of the InAs layer 361A to anexcited state in the conduction band of InAs layer 361A withinsufficient energy to surmount the potential barrier of the conductionband offset to the adjacent GaAs layer 362A. Note that similartransitions can occur in any one of the other 9 periods of InAs (layers361B, 361C, 361D, 361E, 361F, 361G, 361H, 361I, 361J, 361K). Transition327 shows how absorption of a photon with energy in excess of the bandgap of the GaAs layer 362A can also contribute to the photocurrent.Transition 329 shows how absorption of a photon with energy below theband gap of the GaAs layer 362B can contribute to the photocurrent if hetransition takes place between a deep level defect state within the bandgap of layer 362B to above the conduction band edge of layer 362B. Dueto the lattice-mismatch between the alternating InAs and GaAs layers,there were be a high density of misfit and threading dislocations, whichcreate a high density of deep level defect states which will increasethe absorption coefficient for photons with sub-band gap energy. Notethat similar transitions can occur in any one of the other of the GaAsperiods (layers 362A, 362B, 362C, 362D, 362E, 362F, 362G, 362H, 362I,362J, 362K).

Reference is now made to FIG. 3C, showing the band diagram of FIG. 3Bunder bias. The applied bias causes the conduction band edge 388C andvalence band edge 389C to be sloped as shown in the figure. The biascreates an electric field in the i-GaAs regions, which appears as aslope 330 to the conduction band edge of the GaAs regions. Note that theelectric field (and hence slope in the band edges) in the InAs regionsis much smaller, because the applied field is screened by the doping inthe InAs regions. If the electric field 330 is sufficiently high,electrons in these regions can be accelerated to sufficient energy tocause impact ionization and therefore avalanche gain. In addition, eachof the GaAs regions may be made thin enough that the number of impactionization events per pair of InAs/GaAs (NI) junctions is more preciselydeterministic than the number of impact ionization events in bulk GaAs,resulting in a lower excess noise factor.

Reference is now made to FIG. 4A shows an alternative embodimentconsisting of a polycrystalline NIN junction on an amorphous glasssubstrate 401. On top of substrate 401 is deposited n⁺ InAs layer 403,deposited to a thickness 453 of 1000 nm and doped with 1×10¹⁸ cm⁻³silicon atoms. On top of layer 403 is deposited an undoped GaAs layer405A, deposited to a thickness 455A of 20 nm. On top of GaAs layer 405Ais deposited an n⁺ InAs layer 407 deposited to a thickness 457 of 50 nmand doped 1×10¹⁸ cm⁻³ with silicon. This layer structure forms a NINdiode on an amorphous substrate. Due to the shallow donor characteristicof dislocations and grain boundaries in InAs layers 403 and 407 and thedeep level traps of dislocations and grain boundaries in GaAs layer405A, this layer structure exhibits the appropriate NIN sequence ofconductivity. For highest performance, the density of dislocations andpolycrystalline grain boundaries in layer 405A should be relatively low,because conduction along grain boundaries and dislocations generallycause an undesirable leakage current component.

Reference is now made to FIG. 4B, showing a modification to the layerstructure in FIG. 4A that can be advantageously used to lower theconduction along grain boundaries and dislocations. The layer structureis identical, with the exception of layer 405B, which replaces layer405A of FIG. 4A. Layer 405B consists of n⁺ GaAs, deposited to athickness 455B of 20 nm and doped with 1×10¹⁹ cm⁻³ silicon atoms. Thesilicon atoms donate electrons to the conduction band, which then becometrapped at the deep level states of the GaAs. If the doping density oflayer 405B is sufficient to fill a sufficient number of the deep levelstates, conduction through these states can be greatly reduced becauseconduction generally requires the availability of nearby empty states.Therefore, it is desirable to balance the density of deep level stateswith the density of n-type doping to achieve as high an occupancy ofdeep levels as possible.

Reference is now made to FIG. 5A, showing the layer structure of analternative embodiment, consisting of a low temperature growth GaAslayer 505 C grown on a silicon substrate 501. In addition to thedislocations due to the lattice-mismatch between the silicon substrate501 and the GaAs layer 505, low temperature growth GaAs (LTG-GaAs)introduces additional deep level states into the GaAs, which are knownto produce highly insulating GaAs upon anneal. The substrate temperatureduring the growth of layer 505C should be less than about 350° C. topromote the incorporation of excess arsenic during growth, which areincorporated as arsenic antisites and gallium vacancies, both of whichare deep levels. Similar to the case of FIG. 4B, doping of layer 505Cwith 1×10¹⁸ cm⁻³ silicon atoms can be used to increase the occupancy ofdeep levels in the GaAs layer and thereby lower the conductivity throughthe defect states. Additionally, the use of LTG-GaAs allows the use of apost growth anneal to be used to redistribute the excess arsenic in thelayer, and a substantial fraction of the excess arsenic will precipitateinto metallic clusters, which can be used to modify the density of deepstates in the layer. The thickness 555C of layer 505C is 1000 nm. On topof layer 505C is deposited a n⁺ InAs layer 507, grown to a thickness 557of 50 nm and incorporating 1×10¹⁸ cm⁻³ silicon atoms.

Reference is now made to FIG. 5B, showing how the layer structure ofFIG. 5A can be fabricated into a lateral NIN diode. Metallic contacts561A and 561B are deposited on top of layer 507 using conventional metaldeposition techniques. Due to the pinning of the Fermi level in InAs, awide range of metals such as Au, Ni, Al, Ti, Pd, W, etc., readily makelow resistance ohmic contacts to layer 507. Using standardphotolithography techniques, metal contacts 561A and 561B are defined asshown in the figure, with a spacing 563 A between contacts. Next, theportion of InAs layer 507 between the metal contacts 561A and 561B isremoved, eliminating the ohmic conduction path through layer 507 forcontacts 561A and 561B. Conduction between contacts 561A and 561B willtherefore have to include conduction through layer 505C, and thereforethis structure forms a lateral NIN diode. We note here that thisstructure allows formation of NIN diodes on top of crystalline silicon,which can be useful for three dimensional integration applications suchas flash memory. In addition, this lateral NIN diode is suitable as along wavelength photoconductive detector, because the deep levels in theGaAs layer 505C can absorb photons with energies as small as 0.7 eV,similar to transition 325 in FIG. 3B. Thus, this layer structureprovides a means of developing a long wavelength photodetector onsilicon. Very high sensitivity is feasible because the resistivity ofthe defect conduction mechanism can be kept very high by the dopingcompensation technique described in FIG. 4B.

Reference is now made to FIG. 6A, showing the layer structure of analternative embodiment, where a highly defected layer is incorporated asthe gate region of field effect transistor. The structure of a bufferlayer 603 grown on a semi-insulating InP substrate 601 to a thickness of653. The buffer layer is used to promote the growth of the overlyinglayers 605, 607, and 609, and should be made as insulating as possibleto prevent parasitic current flow. Examples of buffer layers compatiblewith substrate 601 are InP and InAlAs grown lattice matched to InP. Aparticularly advantageous buffer layer 603 can be formed from latticematched InAlAs, grown by MBE at a low substrate temperature in order toachieve incorporation of excess As, which causes buffer layer 603 to behighly insulating. The thickness 653 of buffer layer 603 is chosen toachieve the goals of promoting the growth of the overlying layers andproviding a high isolation, and is generally in the range of 100 nm to1000 nm. On top of buffer layer 603 is grown the channel layer 605 whichis grown to a thickness 655. The material in the channel layer 605 ischosen such that it is either lattice matched to buffer layer 603, orthat the lattice mismatch is small enough and the thickness 655 is smallenough to allow the layer to be pseudomorphic and prevent the formationof a significant number of dislocations. In general, layer 605 will beformed from InP, In_(x)Ga_(1-x)As, or In_(y)As_(1-y)P, or InGaAsP, withthe exact material composition chosen to achieve the desired propertiesof mobility, band gap, breakdown strength, saturated drift velocity,band offsets, and other properties know to be advantageous by thoseskilled in the art. On top of layer 605 if grown the wide band gapchannel barrier layer 607, grown to a thickness 657. Layer 607 can beused as a spacer to separate the channel region from the gate, can beused to increase the barrier height to the gate in order to lower gateleakage currents, and can be used as a source of dopants to modulationdope channel region 605. Those skilled in the-art will recognize thatmodulation doping advantageously increases the mobility and free carrierconcentration in the channel region of a FET, and the dopant atomsproviding the modulation doping can be inserted either layer 607, 603,or both. Layer 607 can be formed from any semiconductor that provides asuitable barrier to the channel. In an advantageous embodiment of theinvention, layer 607 can be formed from In_(z)Al_(1-z)As, with z<0.50,with the thickness 657 kept below the pseudomorphic limit to insure thatdislocations generated by the lattice mismatch are not significant.Those skilled in the art will recognize that the strain of the latticemismatch in layer 607 can be made to counterbalance the strain of layer605 to reduce the total strain of the combined layer stack. In anotherembodiment in accordance the invention, layer 607 can be formed forAlGaAs, which will typically be grown to a thickness 657 larger than thepseudomorphic limit and will therefore exhibit a high density ofdislocations, but is capable of isolating channel 605 from gate 609 asshown in FIGS. 1A-1C. On top of the channel barrier layer 607 is grownthe gate layer 609 to a thickness 659. In an advantageous embodiment ofthe invention, gate layer 609 is formed from heavily doped, n-type InAs,which can be made to exhibit high conductivity as well as a largepotential barrier with layer 607, reducing the gate leakage current.

Reference is now made to FIG. 6B, showing how the layer structure ofFIG. 6A can be fabricated into a field effect transistor. Metal gatecontact 662 is deposited on top of gate layer 609, and patterned usingstandard photolithography as shown in the figure. The lateral extent ofthe metal gate contact is 663 A. Because gate layer 609 is chosen fromthose semiconductors that exhibit Fermi level pinning above theconduction band minimum (or below the valence band maximum), it isstraightforward to achieve low resistance ohmic contact to the gatewithout annealing or alloying of the contact. Standard mesa etchingtechniques can be used to define gate mesa 609A and channel barrier mesa607A with lateral extent 663A, which may be self-aligned to gate contact662 simply by using gate contact 662 as the etching mask. Metallicsource contact 661A and drain 661B are deposited directly on top ofchannel layer 605 using conventional metal deposition techniques.Contacts 661A and 661B can be formed using materials that, upon annealwill alloy with channel layer 605, lowering their resistance. In someembodiments, annealing will not be necessary because the surface Fermilevel pinning properties of channel layer 605 readily promote lowresistance ohmic contacts without requiring high temperature annealing.Standard photolithography techniques are used to define the sourcecontacts 661A and drain contact 661B are defined as shown in the figure,with a lateral spacing 663B between contacts. Conduction between sourcecontacts 661A and drain contact 661B can be modulated through fieldeffect modulation of the conductivity of channel 605. Field effectmodulation of the conductivity of channel 605 is achieved by applying abias to gate contact 662, and therefore the structure operates as afield effect transistor.

Reference is now made to FIG. 7A, showing the layer structure of a thinfilm FET structure in accordance with the invention. On top of glasssubstrate 701 is deposited n⁺ InAs channel layer 703, deposited to athickness 753 of 1000 nm and doped n-type with silicon to achieve a freecarrier density of 1×10¹⁷ cm⁻³. On top of channel layer 703 is depositedan undoped GaAs channel barrier layer 705, deposited to a thickness 755of 50 nm. On top of channel barrier layer 705 is deposited an n⁺ InAsgate layer 707, deposited to a thickness 757 of 100 nm and doped n-typewith silicon to a doping density of 1×10¹⁹ cm⁻³.

Reference is now made to FIG. 7B, showing how the layer structure ofFIG. 7A can be fabricated into a FET device. First, gate contact 762 isdeposited on top of n⁺ InAs gate layer 707, and standard lithographictechniques are used to define the gate width 763A as shown in thefigure. Next, gate layer 707 and channel barrier layer 705 are removedfrom the source region 777A and drain region 777B, and source contact761A and drain contact 761B are deposited. Due to the Fermi levelpinning in InAs, contacts 761A, 761B, and 762 can be formed in a widerange of suitable metals, and will readily form low resistive ohmiccontact to their respective layers. Field effect modulation of thechannel 703 conductivity can be achieved by applying a bias to gatecontact 762, effectively modulating the conductivity between sourcecontact 761A and drain contact 761B.

Reference is now made to FIG. 8A, which shows a schematic of a desirableband diagram of a HET in accordance with the invention. The designconstraints of a high performance HET are well known (see Levi andHeiblum references). The y-axis 898 is energy and the x-axis 899 is thevertical depth within the device. Region 809 is the emitter region, 807is the base region, and 805 is the collector region (not to scale). Theconduction band edge is 881, the valence band edge is 883, and the Fermilevel is 882. In the base region 805, the diagram also shows the nextlowest energy conduction band minim in the base region, represented bythe energy level 887. The conduction band offset between the emitterregion 809 and the base region 805 is 891, while the energy differencebetween the emitter band edge and the Fermi level 882 is 891A. Theconduction band offset between the conduction band edge in the baseregion 807 and the conduction band edge in the collector region 805 is895, while the energy difference between the Fermi level 882 and thecollector band edge in the collector region 805 is 895A. Note that inthis simplified representation, no band bending is shown, but in thegeneral case band bending may occur near the junction to accommodate anydifference between the Fermi level positions relative to the vacuumlevel across the junctions. Electrons are injected from the emitter 809into the base 807 with an excess energy determined by 891A. Note thatthe thermal distribution of electrons in emitter layer 809 will actuallyresult in a spread of injected energies that decays exponentially abovethe conduction band energy as a function of kT. To achieve highperformance HET operation, the base-collector barrier height 895 shouldbe significantly lower than conduction band offset 891 at theemitter-base junction, which is used to inject hot electrons from theemitter region 809 into the base region 805, in order to improve thecollection efficiency of the hot electrons in the base. This is becausesome of the hot electrons injected with excess energy 891A will scatterand lose energy as they transit the base region 807. If these electronsthen have an energy less than about 895A at the base-collector junction,they will not have sufficient energy to surmount the base collectorbarrier, and will therefore be lost. Therefore it is desirable to havethe potential barrier height 895 be as low as possible. However, thepotential barrier 895 must be high enough to prevent the injection ofthermal electrons from the base region 807 into the collector region805. Since thermal electrons have a Fermi distribution above the Fermilevel 882, the barrier height 895A should be at least 10 kT above theFermi level 882. In addition the excess energy 891A of electronsinjected into the base 807 should be less than about 893. If the excessenergy 891 is higher than 893, the scattering rate into the alternativeconduction band minimum 887 is increased. Electrons that do scatter intoconduction band minimum 887 will exhibit low mobility, lower velocityand enhanced scattering, reduce the fraction of electrons that transitacross the base with sufficient energy to surmount the base-collectorbarrier 895, and increasing the transit time delay through the baseregion 807.

While the optimizations described above are well known, it is difficultto achieve a high performance band structure as described for FIG. 1because of the limitations of lattice matched materials. Furtherrequirements for high performance include low scattering rates and highconductivity of the base region 807. Low scattering rates increase themean free path of electrons, and allow thicker base regions to be used,while high conductivity reduces the base access resistance and allowsthin base regions to be used, increasing the base transport factor anddecreasing the loss of high energy electrons. In addition, thesemiconductor material used for collector layer 805 should exhibit highelectron transport performance, including high saturated driftvelocities and high breakdown strength. A high saturated drift velocityreduces the transit time for electrons to traverse the collector layer805, while a high breakdown strength enables the use of thin collectorregions without exhibiting avalanche breakdown during operation, whichalso increases the collector transit time. We also note that it issometimes desirable to use thicker collector regions 805 in order todecrease the collector capacitance, because a high collector capacitanceoften lowers the maximum operating frequency. An important trade off canbe made in hot electron transistors—a higher collector capacitance canbe compensated by a lower base resistance, resulting in higherperformance.

The invention solves the limitations of the prior art in several ways:First, it removes certain traditional limits on the choice of materialseligible for the base, emitter, and collector region of a hot electrontransistor, thereby allowing high performance semiconductors such asInAs to be used in the base. Second, it relaxes the constraint requiringa semiconductor emitter to be nearly lattice-matched to the base and/orcollector.

A means of producing high performance, non-lattice-matched semiconductoremitter regions is disclosed. These non-lattice-matched emitters enableHET devices to be produced with higher performance than prior artdevices.

The layer structure of a HET in accordance with the invention is shownin FIG. 8B. The structure is grown on a semi-insulating GaAs substrate801 using conventional epitaxial growth techniques such as molecularbeam epitaxy (MBE) or chemical vapor deposition (CVD). On top ofsubstrate 801 is grown an n-type In_(0.75 Ga) _(0.25)As collector layer803 grown to a thickness 853 of 2.0 μm and doped with silicon to adoping density of 1×10¹⁹ cm⁻³. Thickness 853 was chosen to provide areasonable compromise between processing complexity, layer 803resistance, and defect density at the interface between layers 803 and805. Growing thicker layers decreases this defect density and the layer803 resistance, but increases processing complexity. The In molefraction of layer 803 was chosen to be 75% because this allows growth ofcollector region 805 that is lattice-matched to layer 803. While suchlattice matching is not required, the use of lattice matching betweenlayers 803 and 805 enables layer 805 to exhibit optimal transportproperties, thereby improving transistor performance. Therefore, layer805 consists of undoped In_(0.75Al) _(0.25)As grown to a thickness 855of 1.0 μm. On top of layer 805 is grown the n⁺⁺ InAs base layer 807,grown to a thickness of 857 and doped with silicon to a doping densityof 1×10¹⁹ cm⁻³. While layer 807 is not lattice-matched to layer 857,thickness 855 is below the pseudomorphic limit, which can allow the baseto be a high quality, low defect density single-crystal. On top of layer807 is grown the i-GaAs emitter layer 809 to a thickness 859 of 100 nm.Due to the large lattice-mismatch between layers 807 and layer 809, weexpect lattice relaxation to occur within the first few monolayers ofgrowth, resulting in the generation of a dense network of edge andthreading dislocations near the interface between layers 807 and 809. Asshown in FIGS. 1A, 1B, and 1C, this junction still exhibits excellentrectification characteristics. Finally, on top of layer 809 is grown an⁺⁺ InAs layer 811, doped n-type with silicon to a doping density of1×10¹⁹ cm⁻³ and grown to a thickness 861 of 100 nm. The layer structureof FIG. 8B achieves the desirable band structure of a HET shown in FIG.8A.

Reference is now made to FIG. 9A, which shows another HET structure inaccordance with the invention. Layer 901A is a semi-insulating GaAssubstrate, layer 903A is a n-type In_(0.80)Ga_(0.20)As buffer/contactinglayer grown to a thickness 953A of 2.0 μm, doped n-type with 1×10¹⁸ cm⁻³silicon atoms. On top of layer 903A is grown the collector layer 905A,consisting of a thickness 955A of 1.0 μm of undopedIn_(0.80)Al_(0.20)As. On top of layer 905A is grown the base layer 907Ato a thickness 957A of 20 nm and doped n-type with silicon to a dopingdensity of 1×10¹⁸ cm⁻³. Those skilled in the art will observe thatdifferent base dopings can be used, provided that the base resistanceremains sufficiently low to achieve high frequency operation. In somecases, it may be advantageous to use modulation doping of the base, suchas can be achieved by heavily doping a portion of emitter layer 909An-type, with the free electrons created by the doping being transferredto the InAs base region. Furthermore, we note that very low resistanceohmic contacts can be readily made to the InAs base region due to thehigh electron affinity of InAs, and the Fermi level pinning of InAssurfaces, where the pinning level is above the conduction band edge.This allows nearly any metal to be used for ohmic contacts, and notannealing of the contacts is necessary, which facilitates using verythin base regions, where alloyed contacts have the potential to cause ashort between the base and collector. On top of base layer 905A is grownemitter layer 909A, consisting of undoped GaAs grown to a thickness 959Aof 100 nm. On top of the emitter layer 909A is grown a graded layer911AA, where smooth compositional grading is used to grade fromIn_(0.8)Ga_(0.2)As (near the junction with layer 911AB) to GaAs (nearthe junction with layer 909A). Layer 911AA is undoped and grown to atotal thickness 961AA of 100 nm. On top of layer 911AA is grown a n⁺

In_(0.8)Ga_(0.2)As contacting layer 911AB, grown to a thickness 961AB of100 nm, and doped 1×10¹⁸ cm⁻³ using silicon. Graded layer 911AAfacilitates injection of electrons from contact 911AB into emitter layer909A, and therefore does not rely on the reverse bias breakdowncharacteristics of the junction between layers 909 and 911.

Reference is now made to FIG. 9B, showing another HET structure inaccordance with the invention. This embodiment is identical to thatshown in FIG. 9A, with the exception of the addition of layer 909Bbetween layers 907A and 909A. Layer 909B is an undopedAl_(0.5)Ga_(0.5)As layer grown to a thickness 959B of 10 nm. This layeris used to provide a tunnel barrier between the emitter region 909A andthe base region 907A. The use of a tunnel barrier advantageously reducesthe spread in the direction of the electron velocity of electronsentering the base region 907A, causing the electron trajectory to bemore focused towards collector layer 905A, and reducing the fraction ofelectrons with excessive lateral momentum. Those skilled in the art willrecognize that other tunnel barrier structures may be used, such as adouble barrier resonant tunneling structure. Reference is now made toFIG. 9C, showing a thin film HET in accordance with the invention. Dueto the fact that the invention tolerates lattice-mismatched growth andhigh densities of defects, the invention may be used to make thin filmtransistors using polycrystalline materials. On top of a glass substrate901C is grown an undoped In_(0.75)Ga_(0.25)As layer 903C grown to athickness 953C of 0.5 μm. On top of layer 903C is grown an undopedIn_(0.75)Al_(0.25)As layer 905C grown to a thickness 955C of 0.5 μm. Ontop of layer 905C is grown the InAs base layer 907C to a thickness 957Cof 10 nm. On top of base layer 907C is grown the GaAs emitter layer 909Cgrown to a thickness 959C of 100 nm. On top of emitter layer 909C isgrown the i-In_(0.75)Ga_(0.25)As emitter contacting layer 911C to athickness 961C of 100 nm. Note that the polycrystalline grain boundariesin layer 903C and 911C will exhibit Fermi level pinning positions nearthe conduction band edge, effectively doping the layers n-type. Grainboundaries in layer 907C will exhibit Fermi level pinning positionsabove the conduction band edge, causing this layer to be heavily dopedn-type. Grain boundaries in layers 905C and 909C will pin the Fermilevel near mid-gap, causing these layers to exhibit very low freecarrier concentrations, and can be considered insulating. Somemodification of the doping can be achieved by varying the grain sizes,with larger grain sizes exhibiting less grain boundary surface area, andtherefore lower effective doping. Larger grain sizes may help reduceparasitic leakage currents through layers 905C and 909C, improvingperformance. Those skilled in the art will recognize that doping levelsmay also be modified by using intentional doping, and intentional dopingof layers 905C and 909C may be used to compensate some of the mid gaptrapping levels caused by the grain boundaries, which can be used toreduce parasitic conduction along grain boundaries.

Reference is now made to FIG. 9D, shows an alternative thin film HETstructure in accordance with the invention. On top of substrate 901D isgrown the n-In_(0.8)Ga_(0.2)As collector contact layer 903D to athickness 953D of 0.5 μm and doped with 1'10¹⁹ cm⁻³ silicon atoms. Ontop of layer 903D is grown the i-In_(0.8)Al_(0.2)As collector layer 905Dto a thickness 955D of 0.5 μm and is nominally undoped. On top of layer905D is grown the n⁺ InSb base layer 907D to a thickness 957D of 10 nmand doped 1×10¹⁹ cm⁻³ silicon atoms. On top of layer 907D is grown thei-Al_(0.2)Ga_(0.8)As emitter layer 909 D to a thickness 959 D of 100 nmand is nominally undoped. On top of layer 909 D is grown then-In_(0.8)Ga_(0.2)As emitter layer 911D to a thickness 961D of 100 nmand is doped with 1×10¹⁹ cm⁻³ silicon atoms.

Reference is now made to FIG. 9E, showing another alternative thin filmHET structure in accordance with the invention grown on an amorphousglass substrate 901E. On top of substrate 901E is deposited an aluminummetal collector contacting layer 903E to a thickness 953E of 100 nm. Ontop of layer 903E is grown the i-GaAs collector layer 905E to athickness 955E of 0.5 μm and is nominally undoped. On top of layer 905Eis grown the n⁺ InAs base layer 907E to a thickness 957E of 25 nm anddoped 1×10¹⁷ cm³¹ ³ silicon atoms. On top of layer 907E is grown thei-Al_(0.25)Ga_(0.75)As emitter layer 909E to a thickness 959E of 100 nmand is nominally undoped. On top of layer 909E is deposited an aluminummetal emitter contacting layer 911E to a thickness 961E of 100 nm.

Reference is now made to FIG. 9F, showing another alternative thin filmHET in accordance with the invention. On top of substrate 901F isdeposited a polysilicon layer 903F doped n-type with a doping density of1×10²⁰ cm⁻³ to a thickness 953F of 1000 nm. Those skilled in the artwill recognize that various techniques may be used to improve thequality of polysilicon layer 903F, including flash annealing, laserannealing, hot gas annealing, and various planarization techniques suchas chemical mechanical planarization (CMP). On top of layer 903F isgrown an i-GaAs collector layer 905 F to a thickness 955 F of 1000 nmand is nominally undoped. On top of layer 905F is grown the n⁺ InAs baselayer 907F to a thickness 957F of 10 nm and doped 1×10¹⁹ cm⁻³ siliconatoms. On top of layer 907F is grown deposited a Si₃N₄ emitter layer 909F to a thickness 959 F of 10 nm. To achieve high quality in the emitterlayer 909 F requires a high performance deposition technique such as JetVapor Deposition (T. P. Ma, “Making Silicon Nitride Film a Viable GateDielectric,” IEEE Trans. Electron Devices, v. 45, p. 680 (1998)). On topof layer 909F is deposited an aluminum metal emitter contacting layer911F to a thickness 961F of 100 nm.

1. A heterojunction diode including a first side and a second side, wherein said first side contains at least 10⁷ dislocations and/or grain boundaries per cm².
 2. The heterojunction diode of claim 1 wherein said first side includes a compound semiconductor material containing at least 25% In atoms.
 3. The heterojunction diode of claim 2 wherein said semiconductor material includes atoms from columns III and from column V of the periodic table.
 4. The heterojunction diode of claim 1 wherein said first side contains amorphous semiconductor material.
 5. The heterojunction diode of claim 1 wherein said second side also exhibits a density of dislocations of at least 10⁷ per cm², a density of polycrystalline grains of at least 10⁷ per cm², amorphous semiconductor material, or some combination of these.
 6. A field-effect transistor including a gate electrode, said electrode using at least one heterojunction diode in accordance with claim
 1. 7. A hot-electron transistor including a junction, said junction using a heterojunction diode in accordance with claim
 1. 8. A photodetector including a junction, said junction using a heterojunction diode in accordance with claim
 1. 9. A metal-semiconductor-metal junction wherein said semiconductor exhibits at least 10⁷ dislocations or grain boundaries per cm².
 10. A junction in accordance with claim 9 wherein at least one of said metals is a semi-metal.
 11. A junction in accordance with claim 10 wherein said semi-metal includes at least 25% In atoms.
 12. A diode junction including at least 10⁷ dislocations or grain boundaries per cm², said diode junction acting as a Schottky, a PN, an nN isotype heterojunction, an MIM, an NIN, a PIP, a PIN, or a metal-semiconductor contact.
 13. A diode junction in accordance with claim 12 including amorphous semiconductor material.
 14. A diode junction in accordance with claim 12 including atoms from column III and from column V of the periodic table.
 15. A diode junction in accordance with claim 15 wherein said first side includes at least 25 % In atoms.
 16. A microelectronic device including a plurality of diode junctions in accordance with claim
 12. 17. A transistor in accordance with claim
 16. 18. The transistor of claim 17 wherein said transistor is a MESFET, JFET, HFET, HEMT, pHEMT, or fin FET.
 19. The transistor of claim 17 wherein said transistor is a junction transistor.
 20. The transistor of claim 17 wherein said junction transistor is a BJT, HBT, or metal-base transistor. 